The present invention relates in general to a data reduction circuit for reducing the number of bits of input data digital video signals, and more particularly to a data reduction circuit employing a differential pulse code modulator (DCPM) wherein a time critical loop of said modulator is modified for faster clock operation.
A data reduction circuit of this kind was described by the inventor in an article published in "Proc. IEEE", Vol. 73, No. 4, April 1984, pp. 592 to 598 and which article is incorporated herein by reference. According to that article, the prior art arrangement permits a clock rate of about 10 MHz and can be implemented with a single integrated circuit if 2-/um CMOS technology is used. The maximum possible clock rate of about 10 MHz is too low if such data reduction circuits are to be used in circuits for eliminating flicker in a television picture. This requires higher clock rates which range from about 17 MHz to 20 MHz.
In the prior art arrangement, the time-critical loop, which limits the maximum clock rate, contains a subtractor, an adder, a limiter, a delay element, and a quantizer. This loop must perform the necessary computations within one period of the clock signal, which is only about 100 ns in the prior art arrangement if correspondingly fast adder/subtractor stages are used.
Accordingly, the problem to be solved by the invention is to improve the data reduction circuit so that a shorter computation time corresponding to the intended clock rate of about 17 to 20 MHz is achieved. While the overall circuit is more complicated than the prior art arrangement and contains more subcircuits than the prior art circuit it exhibits improved operation. The advantage, which lies in the solution of the problem, namely, a processing speed about twice that of the prior art arrangement, is achieved, inter alia, by eliminating the need for the adder and limiter in the time-critical loop, so that the latter consists only of the quantizer and subtractor and a delay element. The limiter is placed ahead of the input of the data reduction circuit.
The limiter at the input is designed to reduce the number of bits of the input data as a function of the quantizer characteristic in such a way that during the reconstruction of the sample values within the DPCM loop, a given number of bits, e.g., 8 bits, is not exceeded.
The above-mentioned configuration of the time-critical loop is also the subject matter of European Application No. 85 10 4051.9 corresponding to U.S. Pat. No. 4,713,828. When testing this arrangement, it was discovered that the rounding effects occurring in the two recursive loops with the constant multiplier for 2.sup.-1, which are due to the limitation of the number of bits of the signals, adversely affect the behavior of the data reduction circuit in the presence of input signals showing little variation with time. This results in an increase of the so-called "granular-noise effect". In addition, this impairs the reduction of transmission errors in the receiver.
The present invention provides an arrangement which, using the same configuration of the time-critical loop as in the prior European application, reduces these rounding effects to a tolerable measure. Besides the time-critical loop, there are only signal paths in which two adders or one adder and one subtractor are required between two successive delay elements, which is not the case in the prior arrangement.
Further advantages will become apparent from the following description of the invention taken in conjunction with the accompanying Figures.